1. Field of the Invention
The present invention generally relates to an A/D converter and an A/D converter apparatus and more particularly relates to a parallel A/D converter and an A/D converter apparatus.
2. Description of Related Art
Two types of A/D converters are widely known: successive approximation type A/D converter and flash type A/D converter (parallel A/D converter). FIG. 9 is a block diagram that schematically shows a parallel A/D converter. As shown in FIG. 9, the parallel A/D converter 90 includes a voltage dividing resistor string 91, a plurality of comparators 92 and an encoder 95. The output of the encoder 95 is connected to a digital output terminal 97. The input of the encoder 95 is connected to the plurality of comparators 92. One input terminal of each comparator 92 is connected to an analog input terminal 98 and the other input terminal is connected to one end of each voltage dividing resistor of the voltage dividing resistor string 91. One end of the voltage dividing resistor string 91 is connected to a reference input voltage VREF and the other end is grounded.
The operation of the parallel A/D converter 90 is described below. An analog input voltage VIN input through the analog input terminal 98 is supplied to each comparator. Each comparator compares the analog input voltage VIN with a reference voltage that is divided from the reference input voltage VREF by each voltage dividing resistor in synchronization with a clock CLK. The encoder 95 encodes the analog input voltage VIN into N-bit binary data sequence DOUT according to the output from the comparator 92.
The conversion from the analog value VIN into the digital value DOUT is achieved as a result of the voltage comparison in each comparator and the encoding to the N-bit binary data sequence DOUT in the encoder 95. Such a typical A/D converter is described in 1972 IEEE International Solid-State Circuits Conference, “DIGEST OF TECHNICAL PAPERS” pp 146-148.
The parallel A/D converter 90 needs to have 2N number of comparators to generate the N-bit binary data sequence DOUT. Accordingly, generation of data with a larger number of bits requires a larger circuit size and area. The increase in the area of the A/D converter 90 undesirably leads to an increase in the skew of the analog input voltage VIN due to line delay and the skew of the clock signal CLK due to line delay. If the skews of the voltage VIN and the signal CLK differ, it is difficult for the plurality of comparators to sample the analog signals at the same time. This results in deterioration of the conversion accuracy of the A/D converter 90.
FIG. 10 is a timing chart to describe data errors caused by the difference in skew of the analog input signal VIN and the clock signal CLK. The waveforms indicated by A1, A2, to AM (M=2N) in FIG. 10 show the analog input signals VIN that are input to the comparator in the first stage to the comparator in the Mth stage, respectively. The Mth stage comparator receives the analog signal AM having a phase delayed compared with the signal received by the first-stage comparator due to delay in the signal line. The waveforms indicated by C1 to CM (M=2N) in FIG. 10 show the clock signals CLK that are input to the comparator in the first stage to the comparator in the Mth stage, respectively. The clock that is input to the Mth stage comparator has a phase delayed compared with the clock that is input to the first-stage comparator due to delay in the clock line. As shown in FIG. 10A and FIG. 10B, the larger the number of comparators used in the A/D converter 90 is, the larger a difference between a delay time due to the signal line and a delay time due to the clock line. This causes deviation in the phase of the input signal VIN and the phase of the clock signal CLK, thus failing to sample the input signals of the same time in some cases. This degrades the accuracy of the generated digital signal DOUT.
Though it is possible to adjust the layout to form equal length lines in order to prevent errors due to skew, the drawback can be hardly overcome by merely changing the layout of line length due to the increase in circuit area. It is also possible to place a sample and hold circuit in the previous stage of the A/D converter 90. However, the sample and hold circuit that is compatible with a high-speed operation, which is the characteristics of the parallel A/D converter 90, has a low accuracy. A highly accurate sample and hold circuit cannot follow the high-speed operation. Because of this trade-off, the use of a sample and hold circuit to overcome the drawback of skew is not effective.
As described in the foregoing, the present invention has recognized that the A/D converter apparatus and the A/D converter of the related art cannot achieve high-speed and highly-accurate A/D conversion due to the deviation between the skew of the analog input signal and the skew of the clock signal.